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SINGLE SUPPLY 1:9 PECL/TTL-TO-PECL
ClockWorksTM SY100S811
FEATURES
s s s s s s s s s s s PECL version of popular ECLinPS E111 Low skew Guaranteed skew spec VBB output TTL enable input Selectable TTL or PECL clock input Single +5V supply Differential internal design Similar pin configuration to E111 PECL I/O fully compatible with industry standard Internal 75K PECL input pull-down resistors
DESCRIPTION
The SY100S811 is a low skew 1-to-9 PECL differential driver designed for clock distribution in new, highperformance PECL systems. It accepts either a PECL clock input or a TTL input by using the TTL enable pin TEN. When the TTL enable pin is HIGH, the TTL input is enabled and the PECL input is disabled. When the enable pin is set LOW, the TTL input is disabled and the PECL input is enabled. The device is specifically designed and produced for low skew. The interconnect scheme and metal layout are carefully optimized for minimal gate-to-gate skew within the device. Wafer characterization and process control ensure consistent distribution of propagation delay from lot to lot. Since the S811 shares a common set of "basic" processing with the other members of the ECLinPS family, wafer characterization at the point of device personalization allows for tighter control of parameters, including propagation delay. To ensure that the skew specification is met, it is necessary that both sides of the differential output are terminated into 50, even if only one side is being used. ln most applications, all nine differential pairs will be used and, therefore, terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on the same package side (i.e. sharing the same VCCO as the pair(s) being used on that side) in order to maintain minimum skew. The VBB output is intended for use as a reference voltage for single-ended reception of PECL signals to that device only. When using VBB for this purpose, it is recommended that VBB is decoupled to VCC via a 0.01F capacitor.
s Available in 28-pin PLCC and SOIC packages
BLOCK DIAGRAM
Q0 Q0 Q1 EIN EIN 0 Q2 Q2 Q3 TIN 1 Q3 Q4 Q4 TEN Q5 Q1
PIN CONFIGURATION
VCCO Q1
Q5
Q0 Q0 Q1
Q6 Q6 Q7 Q7 Q8 VBB Q8
VEE TEN EIN VCC EIN VBB TIN
26 27 28 1 2 3 4
25 24 23 22 21 20 19 18 17
Q2 Q2
Q3 Q3 Q4 VCCO Q4 Q5 Q5
TOP VIEW PLCC J28-1
16 15 14 13 12
5
6
7
8
9
10 11
Q7 VCCO
Q8 Q8
Q7 Q6
Q6
Rev.: F
Amendment: /0
1
Issue Date: October, 1998
Micrel
ClockWorksTM SY100S811
PIN CONFIGURATION
TRUTH TABLE
TEN EIN L H X X TIN X X L H Q L H L H
VCC EIN VBB TIN Q8 Q8 Q7 VCCO Q7
1 2 3 4 5 6 7 8 9
28 27 26 25 24 23
EIN TEN VEE Q0 Q0 Q1 VCCO Q1 Q2 Q2 Q3 Q3 Q4 VCCO
L L H H
TOP VIEW SOIC Z28-1
22 21 20 19 18 17 16 15
PIN NAMES
Pin EIN, EIN TIN TEN Q0, Q0 - Q8, Q8 VBB VCC VEE Function Differential PECL Input Pair TTL Input TTL Input Enable Differential PECL Outputs VBB Output PECL VCC (+5.0V) PECL Ground (0V)
Q6 10 Q6 11 Q5 Q5 Q4
12 13 14
PECL DC ELECTRICAL CHARACTERISTICS
VCC = VCCO = +5.0V 5%
TA = 0C Symbol VBB IIH IIL VIH VIL VOH VOL ICC Parameter Output Reference(1) Voltage Input HIGH Current Input LOW Current Input HIGH Input LOW Voltage(1) Voltage(1) Min. 3.62 -- 0.5 3.835 3.190 Typ. -- -- -- -- -- Max. 3.74 150 -- 4.120 3.525 Min. 3.62 -- 0.5 3.835 3.190 TA = +25C Typ. -- -- -- -- -- Max. 3.74 150 -- 4.120 3.525 Min. 3.62 -- 0.5 3.835 3.190 TA = +85C Typ. -- -- -- -- -- Max. 3.74 150 -- 4.120 3.525 Unit V A A V V mV mV mA
Output HIGH Output LOW
Voltage(2) VCC -1025 VCC -955
VCC -870 VCC -1025 VCC -955 VCC -870 VCC -1025 VCC -955 VCC -870
Voltage(2) VCC -1890 VCC -1705 VCC -1620 VCC -1890 VCC -1705 VCC -1620 VCC -1890 VCC -1705VCC -1620 -- 53 65 -- 53 65 -- 60 74
Power Supply(3) Current
NOTES: 1. VCC = VCCO = 5.0V 2. VIN = VIH (Max.) or VIL (Min.) Loading with 50 to VCC -2V. 3. All inputs and outputs open.
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Micrel
ClockWorksTM SY100S811
TTL DC ELECTRICAL CHARACTERISTICS
VCC = VCCO = +5.0V 5%
TA = 0C Symbol VIH VIL IIH IIL VIK
NOTES: 1. VIN = 2.7V 2. VIN = 5.0V 3. VIN = 0.5V 4. IIN = -18mA
TA = +25C Max. -- 0.8 20 100 -0.6 -1.2 Min. 2.0 -- -- -- -- -- Typ. -- -- -- -- -- -- Max. -- 0.8 20 100 -0.6 -1.2 Min. 2.0 -- -- -- -- --
TA = +85C Typ. -- -- -- -- -- -- Max. -- 0.8 20 100 -0.6 -1.2 Unit V V A mA V
Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current(1),(2) Input LOW Current(3) Input Clamp Voltage(4)
Min. 2.0 -- -- -- -- --
Typ. -- -- -- -- -- --
AC ELECTRICAL CHARACTERISTICS(1-6)
VCC = VCCO = +5.0V 5%
TA = 0C Symbol tPLH tPHL Parameter Propagation Delay to EIN (differential)(2) EIN (single-ended)(3) TIN Output(1) 430 330 350 -- Swing(5) Range(6) 250 -1.6 275 -- -- -- 25 -- -- 375 630 730 950 50 -- -0.4 600 430 330 350 -- 250 -1.6 275 -- -- -- 25 -- -- 375 630 730 950 50 -- -0.4 600 430 330 350 -- 250 -1.6 275 -- -- -- 25 -- -- 375 630 730 950 50 -- -0.4 600 ps mV V ps Min. Typ. Max. Min. TA = +25C Typ. Max. Min. TA = +85C Typ. Max. Unit ps
tskew VPP VCMR tr tf
Within-Device skew(4) Minimum PECL Input PECL Common Mode
Output Rise/Fall Times 20% to 80%
NOTES: 1. Part-to-part skew is defined as Max. -- Min. value at the given temperature. 2. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. 3. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. 4. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device. 5. VPP (min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP (min.) is AC limited for the S811, as a differential input as low as 50mV will still produce full PECL levels at the output. 6. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to VPP (min.).
PRODUCT ORDERING CODE
Ordering Code SY100S811JC SY100S811JCTR SY100S811ZC SY100S811ZCTR 3 Package Type J28-1 J28-1 Z28-1 Z28-1 Operating Range Commercial Commercial Commercial Commercial
Micrel
28 LEAD PLCC (J28-1)
Rev. 03
4
Micrel
28 LEAD SOIC .300" WIDE (Z28-1)
Rev. 02
MICREL-SYNERGY
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FAX
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+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated
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